1. Field of the Invention
The present invention relates to multi-layer capacitors, wiring substrates, decoupling circuits, and high-frequency circuits. More particularly, the present invention relates to multi-layer capacitors adapted for improving high-frequency circuits, and wiring substrates, decoupling circuits, and high frequency circuits, which are defined by the multi-layer capacitors.
2. Description of the Related Art
Most conventional multi-layer capacitors are formed of ceramic dielectric materials or the like. Such multi-layer capacitors include a capacitor having a plurality of laminated dielectric layers, a plurality of pairs of mutually opposed first inner electrodes and a plurality of pairs of mutually opposed second inner electrodes alternately disposed in a direction in which the dielectric layers are laminated, the pairs of electrodes opposing via the dielectric layers so as to define a plurality of capacitor units. A first outer terminal electrode is provided on a first end surface of the capacitor, and a second outer terminal electrode is provided on a second end surface thereof. The first inner electrodes are extended out to the first end surface of the capacitor to be electrically connected to the first outer terminal electrode. In addition, the second inner electrodes are extended out to the second end surface of the capacitor to be electrically connected to the second outer terminal electrode.
In the above-described multi-layer capacitor, for example, current flows from the second outer terminal electrode to the first outer terminal electrode, and more specifically, the current flows from the second outer terminal electrode to the second inner electrode, from which the current passes through a dielectric layer to reach the first inner electrode, and then, after passing through the first inner electrode, reaches the first outer terminal electrode.
When the capacitance of a capacitor is indicated by the symbol C, an equivalent series inductance (ESL) is indicated by the symbol L, and the resistance of an electrode referred to as an equivalent series resistance (ESR) is indicated by the symbol R, an equivalent circuit of the capacitor is represented by a circuit in which the capacitance, the equivalent series inductance, and the equivalent series resistance indicated by the symbols C, L, and R, respectively, are connected in series.
In this equivalent circuit, a resonant frequency fo, is equal to a value obtained by an expression 1/ [2xcfx80xc3x97(Lxc3x97C)xc2xd], and the circuit does not function as a capacitor at frequencies higher than the resonant frequency. In other words, when a value of L, that is, the value of ESL is small, the resonant frequency fo is higher, so that the circuit can be used at higher frequencies. Although the use of copper for inner electrodes has been considered in order to reduce the value of ESR, a capacitor having a reduced ESL value is required when the capacitor is used in microwave regions.
In addition, it is also necessary to reduce the ESL value in a capacitor used as a decoupling capacitor connected to a power supply circuit supplying power to an MPU chip as a micro-processing unit contained in a work station, a personal computer, and other such electronic apparatuses including a microprocessor. FIG. 8 is a block diagram illustrating one example of the structure in which an MPU1 and a power supply unit are connected.
In FIG. 8, the MPU 1 has a MPU chip 3 and a memory unit 4. The power supply unit 2 supplies power to the MPU chip 3. A decoupling capacitor 5 is connected to a power supply circuit from the power supply unit 2 to the MPU chip 3. In addition, a signal circuit is disposed on the side of the memory unit 4 extending from the MPU chip 3.
Similar to a typical type of decoupling capacitor, the decoupling capacitor 5 included in the above-described MPU 1 is used for absorbing noise and smoothing power-source fluctuations. Additionally, production of the MPU chip 3, having an operational frequency is over 500 MHz and up to as much as 1 GHz has been recently planned. Regarding such an MPU chip 3, in order to achieve high speed operations, it is necessary to have a fast power supplying function to supply power within a few nano-seconds, from the electrical power charged in a capacitor, when power is immediately needed, for example, during start-up.
Therefore, in the decoupling capacitor 5 used in the MPU 1, it is necessary to have as low an inductance component as possible, for instance, 10 pH or lower. Thus, a capacitor having such a low inductance is needed for such applications.
More specifically, in a certain MPU chip 3 having an operational clock frequency of approximately 500 MHz, a DC power of approximately 2.0 V is supplied, and power consumption is approximately 24 W, that is, it is designed such that a current of about 12 A flows. In order to reduce the power consumption, when an MPU 1 is not operating, a sleep mode in which the power consumption drops to 1 W or lower, is adopted. When converted from a sleep mode to an active mode, power necessary for the active mode needs to be supplied to the MPU chip 3 during the operational clock. For example, at the operational frequency of 500 MHz, when converted from the sleep mode to the active mode, power needs to be supplied within about 4 to 7 nanometer seconds.
However, since it is impossible to supply the above-described power from the power supply unit 2 in time, power is supplied to the MPU chip 3 by releasing the charge stored in the decoupling capacitor 5 disposed in proximity to the MPU chip 3 during the period of time before power from the power supply unit 2 is supplied.
When the operational clock frequency is 1 GHz, in order to satisfy such a function, the ESL value of the decoupling capacitor 5 disposed in proximity to the MPU chip 3 needs to be at least 10 pH or lower.
Since the ESL value of the aforementioned conventional multi-layer capacitor is in a range of approximately 500 pH to 800 pH, it is much higher than the value of 10 pH described above. An inductance component is generated in a multi-layer capacitor because a magnetic flux having direction determined by a direction of current flowing through the multi-layer capacitor is induced, by which a self-inductance component is generated.
Relating to the above-described background, the structures of multi-layer capacitors capable of achieving reduction in ESL are presented in, for example, Japanese Unexamined Patent Publication No. 2-256216, U.S. Pat. No. 5,880,925, Japanese Unexamined Patent Publication No. 2-159008, Japanese Unexamined Patent Publication No. 11-144996, and Japanese Unexamined Patent Publication No. 7-201651.
The aforementioned reduction in ESL is achieved mainly by cancellation of the magnetic flux induced in the multi-layer capacitor. In order to generate such a cancellation of the magnetic flux, the direction of current flowing through the multi-layer capacitor is diversified. In addition, in order to diversify the direction of current, the number of terminal electrodes disposed on an outer surface of the capacitor and the number of parts of inner electrodes extending to be electrically connected to the terminal electrodes are increased, and then, the extended parts of the inner electrodes are arranged to be oriented in various directions.
However, the above-described measures for obtaining a reduced ESL value in the multi-layer capacitor as described above are not yet effective enough. For instance, although a structure in which the inner electrodes are extended out to the two opposing side surfaces of the capacitor is described in Japanese Unexamined Patent Publication No. 2-256216, U.S. Pat. No. 5,880,925, and Japanese Unexamined Patent Publication No. 2-159008, the ESL value can be reduced only down to approximately 100 pH.
Furthermore, in Japanese Unexamined Patent Publication No. 11-144996, although a structure in which the inner electrodes are extended out to the four side surfaces of the capacitor is described, the most effective value of ESL in this case is not lower than 40 pH.
Furthermore, in Japanese Unexamined Patent Publication No. 7-201651, although a structure in which the inner electrodes are extended out to the upper and lower main surfaces of the capacitor is described, the most effective value of ESL in this case is not lower than 50 pH.
Therefore, conventionally, in a high frequency circuit including a power supply line, which is used for an MPU chip incorporating such a multi-layer capacitor, for example, in order to obtain the ESL values of 10 pH or lower, a plurality of multi-layer capacitors connected in parallel must be mounted on a wiring substrate. As a result, an area required for mounting the multi-layer capacitors is greatly increased, which prevents a reduction in costs and size of electronic apparatuses defining such high frequency circuits.
In order to overcome the problems described above, preferred embodiments of the present invention provide a multi-layer capacitor which greatly and effectively reduces an ESL value and to provide a wiring substrate, a decoupling circuit, and a high frequency circuit including such a novel multi-layer capacitor.
According to a first preferred embodiment of the present invention, there is provided a multi-layer capacitor having a capacitor main body including a plurality of laminated dielectric layers. Inside of the capacitor main body, at least one pair of substantially rectangular first inner electrodes and at least one pair of substantially rectangular second inner electrodes which are mutually opposed via specified dielectric layers of the dielectric layers are provided. First outer terminal electrodes and second outer terminal electrodes are disposed on at least one main surface extending substantially parallel to the first and second inner electrodes of the capacitor.
Furthermore, a plurality of first feed-through conductors and a plurality of second feed-through conductors are disposed inside of the capacitor. The first feed-through conductors pass through specified dielectric layers of the plurality of the dielectric layers to electrically connect the first inner electrodes and the first outer terminal electrodes such that the first feed-through conductors are electrically insulated from the second inner electrodes, and the second feed- through conductors pass through specified dielectric layers to electrically connect the second inner electrodes and the second outer terminal electrodes such that the second feed-through conductors are electrically insulated from the first inner electrodes.
The pluralities of the first and second feed-through conductors are distributed over the entire areas of the first and second inner electrodes.
The first and second feed-through conductors are arranged such that the first and second feed-through conductors mutually cancel magnetic fields induced by current flowing through the first and second inner electrodes, and the first and second feed-through conductors are disposed adjacent to each other to be distributed substantially at corners of a square.
In order to solve the aforementioned technological problems, when an alignment pitch of the first and second feed-through conductors is indicated by P and the total number of the first and second feed-through conductors is indicated by N, an arrangement is set such that a ratio of P/N is about 0.085 mm or lower.
Even more preferably, the ratio P/N is no more than about 0.04 mm.
Preferably, in the multi-layer capacitor in accordance with preferred embodiments of the present invention, the first and second outer terminal electrodes are distributed in a dotted configuration corresponding to the first and second feed-through conductors.
Preferably, in this case, a solder bump is provided at each of the first and second outer terminal electrodes.
In addition, in the multi-layer capacitor in accordance with preferred embodiments of the present invention, preferably, the first and second outer terminal electrodes are disposed only on one main surface of the capacitor. Alternatively, the first and second outer terminal electrodes may be disposed on both main surfaces of the capacitor, or the first outer terminal electrodes may be disposed on one main surface of the capacitor and the second outer terminal electrodes may be disposed on the other main surface thereof.
The multi-layer capacitor in accordance with preferred embodiments of the present invention may be arranged to define a decoupling capacitor connected to a power supply circuit for an MPU chip incorporated in a micro-processing unit as an MPU.
In addition, according to another preferred embodiment of the present invention, there is provided a wiring substrate on which one of the above-described multi-layer capacitors is mounted.
As described above, when a multi-layer capacitor according to preferred embodiments of the present invention is applied to a wiring substrate, as one of the specific preferred embodiments, an MPU chip incorporated in a micro-processing unit may be mounted on the wiring substrate. In addition, on the wiring substrate, a power-supply hot-side wiring conductor for supplying a power used for the MPU chip and a ground wiring conductor may be disposed. One of the first outer terminal electrodes and the second outer terminal electrodes of the multi-layer capacitor may be electrically connected to the power-supply hot-side wiring conductor, and the other one of the first outer terminal electrodes and the second outer terminal electrodes may be connected to the ground wiring conductor.
Preferably, the first and second outer terminal electrodes may be each connected to the wiring substrate described above by a bump.
According to another preferred embodiment of the present invention, there is provided a decoupling circuit including one of the novel multi-layer capacitors described above.
According to another preferred embodiment of the present invention, there is provided a high frequency circuit including one of the multi-layer capacitors described above.
Other features, elements, advantages and aspects of the present invention will be described in the following detailed description of preferred embodiments of the present invention with reference to the attached drawings, wherein like reference numerals indicate like elements.